The principles of the present invention have application to various types of non-volatile memories, those currently existing and those contemplated to use new technology being developed. Implementations of the present invention, however, are described with respect to a flash electrically-erasable and programmable read-only memory (EEPROM), wherein the storage elements are floating gates.
During the operation of a non-volatile memory, the reading, writing, and erase of data in one storage unit will often disturb the data stored in other storage units of the memory. One source of these disturbs is the field effect coupling between adjacent floating gates as described in U.S. Pat. No. 5,867,429 of Jian Chen and Yupin Fong, which patent is incorporated herein in its entirety by this reference. Additional techniques for reducing such disturbs are described in U.S. Pat. No. 6,522,580, which is incorporated herein in its entirety by this reference.
This effect and other sources of read and write disturbs are present in various types of flash EEPROM cell arrays. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, 6,151,248, 6,426,893, and 6,512,263.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of such arrays and their operation are given in U.S. Pat. No. 6,522,580, incorporated by reference above. Other examples are given in U.S. patent applications entitled “Highly Compact Non-Volatile Memory and Method Thereof”, by Raul-Adrian Cernea, and “Non-Volatile Memory and Method with Reduced Source Line Bias Errors”, by Raul-Adrian Cemea and Yan Li, both filed Sep. 24, 2002, and in U.S. Pat. Nos. 5,546,341, 5,473,563 and 6,373,746, all hereby incorporated by this reference.
It is still most common in current commercial products for each floating gate to store a single bit of data by operating in a binary mode, where only two ranges of threshold levels of the floating gate transistors are defined as storage levels. The threshold levels of a floating gate transistor correspond to ranges of charge levels stored on their floating gates. In addition to shrinking the size of the memory arrays, the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each floating gate transistor. This is accomplished by defining more than two threshold levels as storage states for each floating gate transistor, four such states (2 bits of data per floating gate) now being included in commercial products. More storage states, such as 16 states per storage element, are contemplated. Each floating gate transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow them to be clearly differentiated from one another. In a multi-state nonvolatile memory, the threshold voltage ranges are often increased in comparison with single-bit memories in order to accommodate the all of the multi-states and their margins. Correspondingly, the voltages applied to the control gates during read and programming are correspondingly increased, resulting in more erase, program, and read disturbs. Additionally, as devices move to lower power designs, the available window in which to fit these multi-states is also shrinking further aggravating the problems.
A common operation of these types of non-volatile memories is to erase blocks of memory cells prior to reprogramming them. The cells within the block are then individually programmed out of erase into states represented by the incoming data being stored. Programming typically includes alternate application to a large number of memory cells in parallel of programming voltage pulses and a reading of their individual states to determine whether the individual cells have reached their intended levels. Programming is stopped for any cell that is verified to have reached its intended threshold level while programming of the other cells being programmed in parallel continues until all of those cells are programmed. When the number of storage states per storage element is increased, the time to perform the programming will usually be increased since the smaller voltage ranges for the individual states requires a greater precision of programming. This can have a significant adverse impact on the performance of the memory systems.
The narrower ranges of the defined floating gate storage levels that result from multi-state operation increases the level of sensitivity of a first group of storage elements to operations performed on a second group of adjacent storage elements. In an erase operation, the storage elements are typically subjected to a large voltage differential in order to remove charge from the floating gate. As non-selected storage elements are often also subjected to high voltage values, through shared word lines, bit lines, well structures, capacitive couplings, or other mechanisms, this can lead to disturbs on the non-selected storage elements. For example, in a NAND structure such as that described in U.S. Pat. No. 6,522,580, incorporated by reference above, a high voltage differential is created across selected storage elements by placing their erase gates at ground and raising the well structure of the array to a high erase voltage. Non-selected storage elements may also be upon this well structure. Although it is common in the prior art to allow unselected erase gates to be charged by capacitive couplings from the well (as is described, for example, in U.S. Pat. No. 5,546,341 incorporated above), there will still be a potential placed across the storage element that can lead to disturbs. If the number of erroneous bits is maintained within the capability of an error correction code (ECC), the errors are corrected but if the number of errors is typically larger than that, some other structural and/or operating technique(s) needs to be employed. It is desired to provide techniques to reduce erase disturbs in non-volatile memories to further increase their performance.